1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more specifically, it relates to a method of fabricating a semiconductor device having an opening filled up with a filler.
2. Description of the Prior Art
As the degree of integration of a semiconductor device is recently increased, a technique of finely working the semiconductor device is becoming increasingly important. Element isolation for isolating semiconductor elements provided in a semiconductor device from each other is known as one of fine working techniques. In this element isolation, a technique referred to as trench isolation is frequently employed following high integration of the semiconductor device.
In this trench isolation, an element isolation trench is formed in a semiconductor substrate and filled up with an insulating material or the like, thereby physically and electrically isolating element regions located on both sides of the trench from each other.
In general, this trench isolation is carried out basically through four steps including a first step of depositing a silicon nitride film on the surface of a silicon substrate through a silicon oxide film, a second step of patterning a part of the silicon nitride film for defining an element isolation region by etching and thereafter forming an element isolation trench through a mask of the patterned part of the silicon nitride film, a third step of thermally oxidizing the surface of the trench and thereafter depositing a silicon oxide film so that the thickness thereof is larger than the total of the depth of the trench and the thickness of the silicon nitride film and a fourth step of performing planarization by polishing and removing the silicon oxide film by chemical mechanical polishing (CMP) through the silicon nitride film serving as a stopper film.
The degree of integration of the semiconductor device can be readily increased due to the aforementioned trench isolation. However, the trench isolation has the following problems:
After the trench is formed, a silicon oxide film, for example, is temporarily deposited in the aforementioned third step for filling up the trench with an insulating material. In this case, a large step (irregularity) may be formed on the surface of the deposited silicon oxide film due to the trench pattern. In other words, a concave portion is formed on a surface part of the silicon oxide film located on the trench while a convex portion is formed on a surface part of the silicon oxide film located on a portion other than the trench. Particularly when the trench has a large opening area, a large step is formed on the surface of the silicon oxide film. In this case, the planarized surface is dispersed in the aforementioned fourth step due to the trench pattern, and hence it is difficult to normally perform planarization. This problem is now described in detail with reference to FIGS. 10 and 11.
In a conventional structure shown in FIG. 10, a trench 105 having a large opening area and trenches 140 having small opening areas are formed on the surface of a silicon substrate 101. Thermal oxide films 107 are formed on the surfaces of the trenches 105 and 140. Silicon nitride films 103 are formed on regions not formed with the trenches 105 and 140 through silicon oxide films 102. The trenches 105 and 140 are filled up with silicon oxide films 150 serving as fillers.
When planarization is performed on the conventional structure shown in FIG. 10 by trench isolation, the surface of the silicon oxide film 150 embedded in the trench 105 after planarization is located downward beyond a part of the upper surface of the silicon substrate 101 located on an element region 130 for defining an active region. In the element region 130 having a large width, a silicon oxide film 131 deposited in the aforementioned third step is neither polished nor removed but remains on the silicon nitride film 103 after planarization. In the conventional element isolation shown in FIG. 10, the surface of the silicon oxide film 131 deposited in the third step is irregularized due to the trench pattern, to disadvantageously result in surface dispersion after planarization.
The aforementioned surface dispersion after planarization results in the following problem: When the silicon nitride films 103 and the silicon oxide films 102 are removed from the state shown in FIG. 10 followed by formation of gate oxide films 120 and a gate electrode 121 as shown in FIG. 11, the gate electrode 121 is formed to cover a step 160 between the silicon oxide film 150 and the surface of the substrate 101. Therefore, field concentration may take place on the step 160 adjacent to the active region, to disadvantageously cause a leakage current between the gate electrode 121 and the active region.
When the silicon nitride films 103 and the silicon oxide films 102 are removed from the state shown in FIG. 10, further, the silicon oxide film 131 remaining on the element region 130 disadvantageously defines a mask to disadvantageously hinder removal of the silicon nitride film 103 and the silicon oxide film 102 located under the same. If the silicon nitride film 103 and the silicon oxide film 102 remain unremoved due to the silicon oxide film 131, the gate electrode 121 is formed on the silicon nitride film 103 as shown in FIG. 11. In this case, the threshold voltage of a transistor is so abnormally increased that the transistor cannot be used.
The aforementioned problems are not restricted to trench isolation but similar problems are caused also in a method of fabricating a semiconductor device comprising a step of filling up an opening such as a trench or a hole with a filler and thereafter planarizing the surface thereof.